/*
 * Copyright (C) 2015 Spreadtrum Communications Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *************************************************
 * Automatically generated C header: do not edit *
 *************************************************
 */

/*
 * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit,
 * Voltage Trimming (4)Ctrl and (5)Bits, Calibration (6)Ctrl and (7)Bits,
 * Voltage (8)Default, Voltage (9)Ctrl and (10)Bits, Voltage Select (11)Count and Voltage (12)List[ ... ...]
 */
    SCI_REGU_REG(vddcore, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_CORE_PD,
	ANA_REG_GLB_DCDC_CORE_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8), 800, 2, 0, 3125);
    SCI_REGU_REG(vddcpu, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_CPU_PD,
	ANA_REG_GLB_DCDC_CPU_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8), 800, 2, 0, 3125);
    SCI_REGU_REG(vddgpu, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_GPU_PD,
	ANA_REG_GLB_DCDC_GPU_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8), 800, 2, 0, 3125);
    SCI_REGU_REG(vddmodem, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_MODEM_PD,
	ANA_REG_GLB_DCDC_MODEM_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8), 800, 2, 0, 3125);
    SCI_REGU_REG(vddmem, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_MEM_PD,
	ANA_REG_GLB_DCDC_MEM_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 1100, 2, 0, 6250);
    SCI_REGU_REG(vddmemq, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_MEMQ_PD,
	ANA_REG_GLB_DCDC_MEMQ_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8), 600, 2, 0, 3125);
    SCI_REGU_REG(vddgen0, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_GEN0_PD,
	ANA_REG_GLB_DCDC_GEN0_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 1875, 2, 20, 9375);
    SCI_REGU_REG(vddgen1, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_GEN1_PD,
	ANA_REG_GLB_DCDC_GEN1_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 1350, 2, 50, 6250);
    SCI_REGU_REG(vddsram, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_SRAM_PD,
	ANA_REG_GLB_DCDC_SRAM_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8), 800, 2, 0, 3125);
    SCI_REGU_REG(avdd18, 0x10, ANA_REG_GLB_POWER_PD_SW, BIT_LDO_AVDD18_PD,
	ANA_REG_GLB_LDO_AVDD18_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), 1775, 2, 1175, 10000);
    SCI_REGU_REG(vddrf1v8, 0x10, ANA_REG_GLB_LDO_VDDRF1V8_REG0, BIT_LDO_VDDRF1V8_PD,
	ANA_REG_GLB_LDO_VDDRF1V8_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), 1775, 2, 1175, 10000);
    SCI_REGU_REG(vddwcn, 0x10, ANA_REG_GLB_LDO_VDDWCN_REG0, BIT_LDO_VDDWCN_PD,
	ANA_REG_GLB_LDO_VDDWCN_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), 900, 2, 900, 15000);
    SCI_REGU_REG(vddcamd1, 0x10, ANA_REG_GLB_LDO_VDDCAMD1_REG0, BIT_LDO_VDDCAMD1_PD,
	ANA_REG_GLB_LDO_VDDCAMD1_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), 1050, 2, 900, 15000);
    SCI_REGU_REG(vddcamd0, 0x10, ANA_REG_GLB_LDO_VDDCAMD0_REG0, BIT_LDO_VDDCAMD0_PD,
	ANA_REG_GLB_LDO_VDDCAMD0_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), 1050, 2, 900, 15000);
    SCI_REGU_REG(vddrf1v25, 0x10, ANA_REG_GLB_LDO_VRF1V25_REG0, BIT_LDO_VDDRF1V25_PD,
	ANA_REG_GLB_LDO_VDDRF1V25_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), 1275, 2, 900, 15000);
    SCI_REGU_REG(avdd12, 0x10, ANA_REG_GLB_LDO_AVDD12_REG0, BIT_LDO_AVDD12_PD,
	ANA_REG_GLB_LDO_AVDD12_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), 1200, 2, 900, 15000);
    SCI_REGU_REG(vddcama0, 0x10, ANA_REG_GLB_LDO_VDDCAMA0_REG0, BIT_LDO_VDDCAMA0_PD,
	ANA_REG_GLB_LDO_VDDCAMA0_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 2800, 2, 1200, 10000);
    SCI_REGU_REG(vddcama1, 0x10, ANA_REG_GLB_LDO_VDDCAMA1_REG0, BIT_LDO_VDDCAMA1_PD,
	ANA_REG_GLB_LDO_VDDCAMA1_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 2800, 2, 1200, 10000);
    SCI_REGU_REG(vddcammot, 0x10, ANA_REG_GLB_LDO_VDDCAMMOT_REG0, BIT_LDO_VDDCAMMOT_PD,
	ANA_REG_GLB_LDO_VDDCAMMOT_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3000, 2, 1200, 10000);
    SCI_REGU_REG(vddsim0, 0x10, ANA_REG_GLB_LDO_VDDSIM0_REG0, BIT_LDO_VDDSIM0_PD,
	ANA_REG_GLB_LDO_VDDSIM0_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3000, 2, 1200, 10000);
    SCI_REGU_REG(vddsim1, 0x10, ANA_REG_GLB_LDO_VDDSIM1_REG0, BIT_LDO_VDDSIM1_PD,
	ANA_REG_GLB_LDO_VDDSIM1_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3000, 2, 1200, 10000);
    SCI_REGU_REG(vddsim2, 0x10, ANA_REG_GLB_LDO_VDDSIM2_REG0, BIT_LDO_VDDSIM2_PD,
	ANA_REG_GLB_LDO_VDDSIM2_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3000, 2, 1200, 10000);
    SCI_REGU_REG(vddemmccore, 0x10, ANA_REG_GLB_LDO_VDDEMMCCORE_REG0, BIT_LDO_VDDEMMCCORE_PD,
	ANA_REG_GLB_LDO_VDDEMMCCORE_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3000, 2, 1200, 10000);
    SCI_REGU_REG(vddsdcore, 0x10, ANA_REG_GLB_LDO_VDDSDCORE_REG0, BIT_LDO_VDDSDCORE_PD,
	ANA_REG_GLB_LDO_VDDSDCORE_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3000, 2, 1200, 10000);
    SCI_REGU_REG(vddsdio, 0x10, ANA_REG_GLB_LDO_VDDSDIO_REG0, BIT_LDO_VDDSDIO_PD,
	ANA_REG_GLB_LDO_VDDSDIO_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3000, 2, 1200, 10000);
    SCI_REGU_REG(vdd28, 0x10, ANA_REG_GLB_POWER_PD_SW, BIT_LDO_VDD28_PD,
	ANA_REG_GLB_LDO_VDD28_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 2800, 2, 1200, 10000);
    SCI_REGU_REG(vddwifipa, 0x10, ANA_REG_GLB_LDO_VDDWIFIPA_REG0, BIT_LDO_VDDWIFIPA_PD,
	ANA_REG_GLB_LDO_VDDWIFIPA_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3300, 2, 1200, 10000);
    SCI_REGU_REG(vdddcxo, 0x10, ANA_REG_GLB_POWER_PD_SW, BIT_LDO_VDD18_DCXO_PD,
	ANA_REG_GLB_LDO_VDD18_DCXO_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 1800, 2, 1200, 10000);
    SCI_REGU_REG(vddusb33, 0x10, ANA_REG_GLB_LDO_VDDUSB33_REG0, BIT_LDO_VDDUSB33_PD,
	ANA_REG_GLB_LDO_VDDUSB33_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3300, 2, 1200, 10000);
    SCI_REGU_REG(vddldo0, 0x10, ANA_REG_GLB_LDO_VDDLDO0_REG0, BIT_LDO_VDDLDO0_PD,
	ANA_REG_GLB_LDO_VDDLDO0_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 2800, 2, 1200, 10000);
    SCI_REGU_REG(vddldo1, 0x10, ANA_REG_GLB_LDO_VDDLDO1_REG0, BIT_LDO_VDDLDO1_PD,
	ANA_REG_GLB_LDO_VDDLDO1_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 1800, 2, 1200, 10000);
    SCI_REGU_REG(vddldo2, 0x10, ANA_REG_GLB_LDO_VDDLDO2_REG0, BIT_LDO_VDDLDO2_PD,
	ANA_REG_GLB_LDO_VDDLDO2_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), 3300, 2, 1200, 10000);
